dram refresh

基本解释

The refresh cycles are usually performed by a peripheralcalled a DRAM controller.
刷新周期一般由一个叫DRAM控制器的外设完成。
It is mainly composed of DMA controller (82C37), interrupt controller (82C59), programmable interval timers(82C54), DRAM refresh control, wait state generator and system reset logic.
其内部主要由DMA控制器（82C37）、中断控制器（82C59）、可编程间隔计时器（82C54），DRAM刷新控制器，等待状态产生器，系统重置电路组成。
Once data has been written in DRAM, charges stored in each capacitor must maintain more than the refresh time so that the information stored in each DRAM cell can be read out correctly.
数据一旦被写进DRAM，每个小电容上电荷的存储时间就必须大于DRAM的刷新脉冲时间，如果由于漏电流致使存储的电荷丢失，就会导致数据读取的误操作。