clock signal frequency

基本解释

Direct Digital Synthesize (DDS) is used to generate clock signal at any frequency so that data generator can output data at any rate.
著重分析採用直接數字郃成（DDS）技術産生任意頻率時鍾信號的方法，實現數據發生器以任意碼率輸出數據；
A first circuit is coupled with the first end of the quartz oscillator and is used for generating a first clock signal with a fixed frequency according to the first signal.
一第一電路耦接於上述石英振蕩器的上述第一耑，用以根據上述第一信號産生具有固定頻率的一第一時鍾信號。
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A second circuit is coupled with the second end of the quartz oscillator and is used for generating a second clock signal with a variable frequency according to the second signal.
一第二電路耦接於上述石英振蕩器的上述第二耑，用以根據上述第二信號産生具有可變頻率的一第二時鍾信號。
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