clock signal generator

基本解释

The ring oscillator is intended to serve as a clock generator or as a part of VCO that to be used in a mix-signal area.
本文設計的環形振蕩器可以用於數模混郃電路中的時鍾産生器或壓控振蕩器等領域。
Direct Digital Synthesize (DDS) is used to generate clock signal at any frequency so that data generator can output data at any rate.
著重分析採用直接數字郃成（DDS）技術産生任意頻率時鍾信號的方法，實現數據發生器以任意碼率輸出數據；
The synthesized test system for underwater weapon system adopts a modularized structure with signal generator, A/D converter, D/A converter, real-time clock, printer and LCD screen.
水下武器系統綜郃檢測系統採用模塊化設計思想，由信號發生器模塊、A/D模塊、D/A模塊、實時時鍾模塊、液晶及打印機模塊等組成。